Anúncio de Duas Palestra Apoiadas pelo IEEE no PPGCC (dias 19 e 20 de dezembro)

15/12/2019 15:51

Nos dias 19 e 20 de dezembro próximos ocorrerão palestras sobre compressão de vídeo (video coding), com o apoio do IEEE CASS RS Chapter, do IEEE CEDA Brazil Chapter e do PPGCC/UFSC. Os detalhes das palestra estão logo abaixo. Todos os interessados estão convidados.

Obs: as palestras serão em língua portuguesa.

Talk # 1:

Title: Introduction to the Versatile Video Coding (VVC) standard: new tools and comparison with HEVC

Speaker: Prof. Dr. Guilherme Corrêa (Universidade Federal de Pelotas – UFPel)

Date/time: Dec. 19, 2019 (Thursday), 14:00

Room: INE 105 (Auditório do INE)

Sponsorship: IEEE Council on Electronic Design Automation (CEDA) e PPGCC/UFSC



The increasing demand for high-definition and ultra-high-definition video content, as well as for immersive multimedia experience such as 3D/360º video and virtual/augmented/mixed reality requires that even more efficient compression tools are developed and incorporated to future video coding standards. The Versatile Video Coding (VVC) standard is currently under development and is expected to be finalized in 2020, with several new tools and features that allow compression efficiency levels beyond the achieved by its predecessor, the High Efficiency Video Coding (HEVC) standard. The main goal of this talk is to present an overview of the main tools introduced by VVC, especially focusing on inter-frame and intra-frame prediction. Besides, the talk will also present the authors’ ongoing research related to VVC, which includes a complexity analysis and comparison between VVC and HEVC and the development of complexity reduction strategies for VVC based on supervised machine learning.

Speaker’s Short-bio: 

Prof. Guilherme Correa received the Ph.D. degree in Electrical and Computer Engineering from the University of Coimbra – Portugal in 2015, the Master degree in Computer Science from the Federal University of Rio Grande do Sul – Brazil in 2010 and the Bachelor degree in Computer Science from the Federal University of Pelotas – Brazil in 2008. Currently, he is a professor at the Federal University of Pelotas – Brazil and a researcher with the Video Technology Research Group (ViTech) and the Group of Architectures and Integrated Circuits (GACI). His research interests include image and video coding/transcoding, point cloud compression, learning-based image/video compression, multimedia transport and delivery and digital systems design.

Talk # 2:

Title: Approximate Hardware Accelerators for Video Coding

Speaker: Prof. Dr. Cláudio Diniz (Universidade Católica de Pelotas – UCPel)

Date/time: Dec. 20, 2019 (Friday), 15:00

Room: INE 105 (Auditório do INE)

Sponsorship: IEEE Circuits and Systems Society (CASS), RS Chapter & PPGCC/UFSC

Abstract: Power density in recent nanometer-sized semiconductor manufacturing technologies has reached a critical level, limiting the operating frequency of digital circuits and the number of transistors that can switch at the maximum frequency. Such limitations establish an upper bound on the performance of multi-core general purpose processors. At the same time, recent video coding standards, e.g. High Efficiency Video Coding (HEVC) and the emerging Versatile Video Coding (VVC), which enables ultra-high resolution videos and new video applications such as 360º video, lead to a growing increase in the computational effort of video coding systems. This talk presents some solutions to these challenges related to developing dedicated hardware accelerators for video encoder modules with approximate computing techniques.

Speaker’s Short Bio: Cláudio Diniz received the Computer Engineering degree from Universidade Federal do Rio Grande (FURG), and the Master and Doctor degrees in Computer Science from Universidade Federal do Rio Grande do Sul (UFRGS). He is a Professor at Universidade Católica de Pelotas (UCPel). His research interests are in the field of microelectronics, image processing and embedded systems, with special focus on the design of hardware accelerators and integrated circuits for video coding. He is an IEEE Member (CASS, CEDA, SPS, SSCS) and acts as Activities Coordinator of the IEEE Circuits and Systems Society (CASS) Rio Grande do Sul Chapter.